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Teradyne Nextest FPGA Team is looking for experienced verification engineer with passion to drive the product design quality to the highest level and contribute to company’s product success story. The verification engineer will be responsible for the planning, strategy, and execution of challenging FPGA verification projects and work under the technical supervision of a Verification Lead.
Job Responsibility:
Understand the design requirements from verification perspective
Functional verification using System Verilog and UVM methodology
Create testbench, verification components, and tests
Create self-checking verification environment with data checkers and assertions
Debug failures using waveforms and test log reports
Drive verification completion with 100% functional coverage and code coverage
Interacting with FPGA design, software and hardware team for test strategies and debugging failures
Requirements:
BS in Computer Science, Computer Engineering or Electrical Engineering or related field
English proficiency
5 years of experience with Digital Design functional verification
5 years of experience with Industry standard protocols (e.g. PCIE, AXI)
5 years of experience with EDA Tools (e.g. Cadence Xcelium, Simvision)
5 years of experience with System Verilog
5 years of experience with UVM (Testbench components, development)
5 years of experience with Verification IP integration
Nice to have:
MS degree in Computer Science, Computer Engineering or Electrical Engineering
Excellent oral, written, and presentation skills
Energetic team player who can work with a variety of people & disciplines