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Substrate IC Package Layout Design Engineer

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Etched

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Location:
United States , San Jose

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Category:
IT - Software Development

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Contract Type:
Not provided

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Salary:

150000.00 - 275000.00 USD / Year
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Job Description:

As a Substrate IC Package Layout Design Engineer you will be responsible for the end-to-end design of complex IC substrate packages, supporting high-power consumption and high-speed signaling. The ideal candidate will have extensive experience with large substrate designs (>50mm), complex power delivery networks, and high-speed signaling solutions (up to and beyond 50GHz). You will work closely with silicon, signal integrity, power integrity, and system help co-design world class substates with OSAT providers. Intense focus on optimization for power delivery through substrate, pushing what’s possible.

Job Responsibility:

  • IC Substrate Layout Design: Lead the design and development of complex IC substrate layouts for high-power AI processors and accelerators
  • Design large (>50mm) and complex multi-layer substrate packages with high pin counts and dense routing requirements
  • Ensure robust power delivery designs capable of supporting >700W custom silicon solutions
  • High-Speed Signal Routing & Integrity: Develop high-speed signal routing solutions capable of supporting >50GHz signaling while minimizing signal integrity issues such as loss and crosstalk
  • Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and implement solutions in substrate layout
  • Advanced Packaging & CoWoS Integration: Optimize CoWoS (Chip-on-Wafer-on-Substrate) interposer designs for thermal and electrical performance
  • Work closely with chip design, packaging, and manufacturing teams to ensure design feasibility and manufacturability
  • Design Validation & Verification: Perform DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification for all substrate designs
  • Develop and maintain design documentation and guidelines for future substrate designs
  • Support design reviews and provide technical guidance to junior team members

Requirements:

  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
  • 10+ years of experience in IC substrate layout design for high-performance processors or accelerators
  • Extensive experience with large substrate packages (>50mm) and complex high-density layouts
  • Proven experience with high-power (700W+) package designs and robust power delivery networks
  • Expertise in high-speed signaling design (>50GHz) and mitigating signal integrity challenges (crosstalk, reflections, impedance mismatches)
  • Strong experience with CoWoS (Chip-on-Wafer-on-Substrate) interposer design and the impact of the substrate design to support CoWos
  • Advanced proficiency in Allegro Package Designer (including constraint management, routing, and design verification)
  • Deep understanding of SI/PI principles and how they apply to package-level design
  • Strong analytical skills and ability to work effectively in a fast-paced, cross-functional team environment
What we offer:
  • Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
  • Housing subsidy of $2k per month for those living within walking distance of the office
  • Relocation support for those moving to San Jose (Santana Row)
  • Various wellness benefits covering fitness, mental health, and more
  • Daily lunch + dinner in our office

Additional Information:

Job Posted:
February 18, 2026

Employment Type:
Fulltime
Work Type:
On-site work
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