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At Boeing, we innovate and collaborate to make the world a better place. We’re committed to fostering an environment for every teammate that’s welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us. Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for a Static Timing Analysis (STA) Engineer to join us as part of our Boeing Electronic Products team located in El Segundo, CA and at the heart of Boeing’s products - ASICs and FPGAs.
Job Responsibility:
Responsible for STA analysis and convergence throughout the ASIC cycle
Responsible for finding solution for intricate timing paths (Digital, analog and mixed signal)
Facilitate STA methodology in collaboration with other STA leaders
Generate timing constraints for multiple ASICs and FPGAs
Generate tool independent timing constraints that will work for synthesis, place & route and static timing analysis
Responsible for intricate cross domain timing path closure
Extract timing information from circuit analysis and develop primary input setup/hold timing constraints as well as primary output required arrival time (RAT) and skew timing constraints
Programming skills with Python, TCL, Perl, Unix shell etc.
Help train new engineers
Requirements:
Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
5 years of experience with timing closure on ASICs and FPGAs
Experience with several ASICs/FPGAs signoff and at least one ASIC tape-out. Good understanding of RTL to GDS flow
Proficiency using Synopsys Primetime (or Cadence Tempus) for timing analysis and Synopsys Design Compiler (or Cadence Genus) for synthesis
Ability to work with large physical design team to make the timing convergence successful
This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret, Top Secret, or Top-Secret SCI Clearance Post-Start is required.
Nice to have:
Lead, Level 5: 15+ years of related work experience or an equivalent combination of education and experience
10 or more years of experience with timing closure on ASICs and FPGAs
Experience in using multiple static timing tools (Cadence Tempus, Vivado, Synopsys Primetime)
Fair knowledge of Synopsys Fusion Compiler, Formality (Cadence LEC), and other relevant tools (e.g. TCM, Fishtail)
Synopsys physical design AI tool experience is a plus
Experience leading static timing closure and training new hires
Familiarity with space-based design techniques and radiation mitigation
Understanding of design for testability (DFT) and its implications on timing
Capable of working independently, self starter
Proficiency with multiple scripting languages (Python, C SHELL, TCL)
Capable of handling timing closure on multiple designs simultaneously
What we offer:
Relocation based on candidate eligibility
Opportunity to enroll in a variety of benefit programs, generally including health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and a number of programs that provide for both paid and unpaid time away from work
Generous company match to your 401(k)
Industry-leading tuition assistance program pays your institution directly
Fertility, adoption, and surrogacy benefits
Up to $10,000 gift match when you support your favorite nonprofit organizations