CrawlJobs Logo

Static Timing Analysis (STA) Engineer

boeing.com Logo

Boeing

Location Icon

Location:
United States , El Segundo

Category Icon

Job Type Icon

Contract Type:
Not provided

Salary Icon

Salary:

146200.00 - 239200.00 USD / Year
Save Job
Save Icon
Job offer has expired

Job Description:

At Boeing, we innovate and collaborate to make the world a better place. We’re committed to fostering an environment for every teammate that’s welcoming, respectful and inclusive, with great opportunity for professional growth. Find your future with us. Boeing Space, Intelligence & Weapons Systems has an exciting opportunity for a Static Timing Analysis (STA) Engineer to join us as part of our Boeing Electronic Products team located in El Segundo, CA and at the heart of Boeing’s products - ASICs and FPGAs.

Job Responsibility:

  • Responsible for STA analysis and convergence throughout the ASIC cycle
  • Responsible for finding solution for intricate timing paths (Digital, analog and mixed signal)
  • Facilitate STA methodology in collaboration with other STA leaders
  • Generate timing constraints for multiple ASICs and FPGAs
  • Generate tool independent timing constraints that will work for synthesis, place & route and static timing analysis
  • Responsible for intricate cross domain timing path closure
  • Extract timing information from circuit analysis and develop primary input setup/hold timing constraints as well as primary output required arrival time (RAT) and skew timing constraints
  • Programming skills with Python, TCL, Perl, Unix shell etc.
  • Help train new engineers

Requirements:

  • Bachelor of Science degree in Engineering (with a focus in Electrical, Mechanical or Aeronautical), Computer Science, Data Science, Mathematics, Physics, Chemistry or non-US equivalent qualifications directly related to the work statement
  • 5 years of experience with timing closure on ASICs and FPGAs
  • Experience with several ASICs/FPGAs signoff and at least one ASIC tape-out. Good understanding of RTL to GDS flow
  • Proficiency using Synopsys Primetime (or Cadence Tempus) for timing analysis and Synopsys Design Compiler (or Cadence Genus) for synthesis
  • Ability to work with large physical design team to make the timing convergence successful
  • This position requires the ability to obtain a U.S. Security Clearance for which the U.S. Government requires U.S. Citizenship. An interim and/or final U.S. Secret, Top Secret, or Top-Secret SCI Clearance Post-Start is required.

Nice to have:

  • Lead, Level 5: 15+ years of related work experience or an equivalent combination of education and experience
  • 10 or more years of experience with timing closure on ASICs and FPGAs
  • Completed multiple first-pass success ASIC tape-outs with intricacies (Cross clock domain, async crossing etc.)
  • Experience in using multiple static timing tools (Cadence Tempus, Vivado, Synopsys Primetime)
  • Fair knowledge of Synopsys Fusion Compiler, Formality (Cadence LEC), and other relevant tools (e.g. TCM, Fishtail)
  • Synopsys physical design AI tool experience is a plus
  • Experience leading static timing closure and training new hires
  • Familiarity with space-based design techniques and radiation mitigation
  • Understanding of design for testability (DFT) and its implications on timing
  • Capable of working independently, self starter
  • Proficiency with multiple scripting languages (Python, C SHELL, TCL)
  • Capable of handling timing closure on multiple designs simultaneously
What we offer:
  • Relocation based on candidate eligibility
  • Opportunity to enroll in a variety of benefit programs, generally including health insurance, flexible spending accounts, health savings accounts, retirement savings plans, life and disability insurance programs, and a number of programs that provide for both paid and unpaid time away from work
  • Generous company match to your 401(k)
  • Industry-leading tuition assistance program pays your institution directly
  • Fertility, adoption, and surrogacy benefits
  • Up to $10,000 gift match when you support your favorite nonprofit organizations

Additional Information:

Job Posted:
January 07, 2026

Expiration:
January 24, 2026

Employment Type:
Fulltime
Work Type:
On-site work
Job Link Share:

Looking for more opportunities? Search for other job offers that match your skills and interests.

Briefcase Icon

Similar Jobs for Static Timing Analysis (STA) Engineer

Silicon Design Engineer

Be part of AMD IO IP team, joining IP design work on host controller IP for the ...
Location
Location
Taiwan , Hsinchu; Taipei
Salary
Salary:
Not provided
amd.com Logo
AMD
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Expert in Static Timing Analysis, familiar with DC, PT, GCA, and commands, worked in timing closure tasks with high clock frequency
  • Expert in Verilog RTL design on large-scale digital IP
  • Good English communication, presentation, and documentation
  • Work is performed with limited supervision. Strong sense of task scheduling and delivering on time as predetermined milestones committed to the manager
  • Can solve complex, novel, and non-recurring problems
  • Major in EE, CS or related, Master Degree or Bachelor with solid working experiences
Job Responsibility
Job Responsibility
  • Takes part in host controller development based on architectural requirements for next-generation IO
  • Works on STA tasks such as defining clock architecture, creating SDC and exceptions, and analyzing timing reports
  • Works on RTL code development for IP blocks in Verilog HDL to ensure functionality is correct and reusable for multiple product lines
  • Deals with complex problems in both STA and RTL
  • Makes technical decisions
  • Coaches and mentors junior staff
Read More
Arrow Right

Staff Engineer, ASIC Development Engineering (STA)

We are seeking a highly skilled and experienced Staff Engineer for our Static Ti...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
  • A minimum of 5 years of experience in Static Timing Analysis
  • Proven track record of successfully executing STA
  • In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus, Constraints Manager) and methodologies
  • Strong understanding of digital design principles, physical design, and semiconductor fabrication processes
  • Excellent problem-solving skills and the ability to think strategically and analytically
  • Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders
  • Ability to prioritize tasks and manage multiple project work simultaneously
  • A proactive, results-oriented mindset with a passion for innovation and continuous improvement
Job Responsibility
Job Responsibility
  • Own Subsystem level STA, providing direction and guidance to PnR team for Timing closure & Synthesis report analysis
  • Work with IP & Design team for Timing constraints Development & Review activities
  • Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs
  • Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance
  • Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes
  • Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance
  • Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the team’s workflow
  • Prepare and present detailed timing reports and technical documentation to stakeholders
  • Foster a culture of innovation, collaboration, and continuous improvement within the STA team
  • Fulltime
Read More
Arrow Right

Staff Engineer, ASIC Development Engineering (STA)

We are seeking a highly skilled and experienced Staff Engineer for our Static Ti...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
  • A minimum of 5 years of experience in Static Timing Analysis
  • Proven track record of successfully executing STA
  • In-depth knowledge of STA tools (e.g., Synopsys PrimeTime, Cadence Tempus , Constraints Manager) and methodologies
  • Strong understanding of digital design principles, physical design, and semiconductor fabrication processes
  • Excellent problem-solving skills and the ability to think strategically and analytically
  • Exceptional communication and interpersonal skills, with the ability to effectively collaborate with cross-functional teams and stakeholders
  • Ability to prioritize tasks and manage multiple project work simultaneously
  • A proactive, results-oriented mindset with a passion for innovation and continuous improvement
  • Experience with advanced process nodes (e.g., 7nm, 5nm) is highly desirable
Job Responsibility
Job Responsibility
  • Own Subsystem level STA , providing direction and guidance to PnR team for Timing closure & Synthesis report analysis
  • Work with IP & Design team for Timing constraints Development & Review activities
  • Develop and implement advanced STA methodologies and strategies to meet the timing closure requirements of complex IC designs
  • Collaborate with cross-functional teams, including design, verification, physical design, and DFT, to ensure seamless integration and optimal timing performance
  • Drive the development and maintenance of STA scripts and tools to automate and streamline timing analysis processes
  • Conduct thorough timing analysis, identify critical paths, and develop strategies to mitigate timing violations and improve overall design performance
  • Stay abreast of industry trends and emerging technologies in STA and related fields, and incorporate best practices into the team’s workflow
  • Prepare and present detailed timing reports and technical documentation to stakeholders
  • Foster a culture of innovation, collaboration, and continuous improvement within the STA team
  • Fulltime
Read More
Arrow Right
New

Technologist, ASIC Development Engineering (PD Methodology & CAD Flow Architect/Lead)

Sandisk’s ASIC team builds state-of-the-art memory controllers that power world-...
Location
Location
India , Bengaluru
Salary
Salary:
Not provided
sandisk.com Logo
Sandisk
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 10+ years of experience in Physical Design, PD Methodology, or CAD for advanced ASICs
  • Deep, hands-on understanding of complete PD flow, including: Synthesis, Logical Equivalence Checking (LEC), DFT insertion and integration, Place & Route, Static Timing Analysis (STA), Physical Verification, EM/IR analysis
  • Strong grasp of inter-dependencies across the PD flow and their impact on design convergence and PPA
  • Proven experience architecting PD methodologies and flows for complex SoCs or IPs on advanced nodes
  • M.Tech in VLSI Design or a related field (or equivalent industry experience)
  • Proficiency in scripting and automation using TCL, Perl, and/or Python
  • Experience working in multi-project, high-complexity environments with tight schedules
Job Responsibility
Job Responsibility
  • Lead and mentor the PD Methodology/CAD team to deliver scalable, production-ready flows and innovative solutions across multiple programs
  • Design and architect end-to-end PD methodologies (RTL to GDS) for advanced technology nodes, ensuring correctness, robustness, and scalability
  • Drive continuous improvement in PPA (Power, Performance, Area) and turnaround time through flow optimization, automation, and best practices
  • Work closely with foundry partners to understand node-specific challenges (design rules, variability, EM/IR, signoff requirements) and develop correct-by-construction solutions
  • Collaborate with IP teams, RTL design, DFT, and signoff teams to address cross-domain optimization challenges and enable smooth design convergence
  • Develop “shift-left” and “push-up” methodologies to detect and resolve issues early in the design cycle, improving predictability and schedules
  • Deliver high-quality, signoff-clean flows with strong emphasis on reliability, yield, and manufacturability
  • Leverage AI/ML techniques to improve quality, debug efficiency, predict design issues, and enhance overall productivity
  • Foster a culture of technical excellence and innovation, encouraging the team to develop novel solutions for next-generation challenges
  • Fulltime
Read More
Arrow Right

Senior SoC/ASIC Physical Design Engineer

As a Senior SoC/ASIC Physical Design Engineer, you will work on developing and i...
Location
Location
United States , Irvine
Salary
Salary:
Not provided
xcelerium.com Logo
Xcelerium
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 5+ years of ASIC and/or physical design flow development experience
  • Experience with ASIC physical design, physical design flows and methodologies (i.e., synthesis, place and route, STA, formal verification, CDC or power analysis using industry standard tools)
  • Scripting experience with Python, Tcl, or Perl
  • Experience in extraction of design parameters, QOR metrics, analyzing trends, voltage scaling (SVS, DVFS), and SRAM split rail implementation
  • Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
  • Strong experience with Synopsys EDA tools including understanding of their capabilities and underlying algorithms
  • Strong knowledge of deep sub-micron FinFET and CMOS solid state physics
  • Strong knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
  • Deep understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
  • Familiar with CMOS analog circuit and physical design
Job Responsibility
Job Responsibility
  • Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
  • Develop/improve physical design methodologies and automation scripts for various implementation steps
  • Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
  • Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution/timing/congestion and flow issues, identify potential solutions and drive execution
  • Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop
  • Fulltime
Read More
Arrow Right

Asic Engineer, Implementation

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologie...
Location
Location
United States , Sunnyvale
Salary
Salary:
166000.00 - 198220.00 USD / Year
meta.com Logo
Meta
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor's degree (or foreign degree equivalent) in Electronics Engineering, Computer Engineering, Computer Science, Analytics, or related field and 3 years of work experience in the job offered or related occupation
  • Requires 3 years of experience in the following skills: Front End Design Integration
  • RTL design using Verilog
  • RTL Physical Synthesis and design optimization for Power, Performance, Area
  • Knowledge of front-end and back-end ASIC tools
  • Floor planning for I/O, Hard Macros
  • Writing Timing Constraints for Block Synthesis, Timing
  • Using Synthesis Tools (Design Compiler, Genus)
  • Using Physical Design Tools (Innovus, ICC)
  • Using Static Timing Tools (Primetime)
Job Responsibility
Job Responsibility
  • Run Logic/Physical Synthesis using advanced optimization techniques and generate optimized Gate Level Netlist for Timing, Area, Power
  • Debug the timing/area/congestion issues and work with RTL & Physical designers to resolve them
  • Perform Power Estimation at RTL and Gate Level and identify power reduction opportunities
  • Run Formal Verification checks between RTL and Gate level netlist and debug the aborts, inconclusive and Logic Equivalency failures
  • Perform RTL Lint and work with the Designers to create waivers
  • Perform RTL Clock Domain Crossing Analysis and do block level CDC signoff
  • Perform RTL Reset Domain Crossing Analysis and do block level RDC signoff
  • Perform RTL DFT Analysis and improve the DFT coverage for Stuck-at faults
  • Develop Timing Constraints for RTL-Synthesis and PrimeTime-STA for the blocks and the top-level including SOC
  • Analyze the inter-block timing and come up with IO budgets for the various partition blocks
What we offer
What we offer
  • bonus
  • equity
  • benefits
Read More
Arrow Right

Senior SoC/ASIC Physical Design Engineer

As a Senior SoC/ASIC Physical Design Engineer, you will work on developing and i...
Location
Location
United States , Irvine
Salary
Salary:
Not provided
xcelerium.com Logo
Xcelerium
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • 5+ years of ASIC and/or physical design flow development experience
  • Experience with ASIC physical design, physical design flows and methodologies (i.e., synthesis, place and route, STA, formal verification, CDC or power analysis using industry standard tools)
  • Scripting experience with Python, Tcl, or Perl
  • Experience in extraction of design parameters, QOR metrics, analyzing trends, voltage scaling (SVS, DVFS), and SRAM split rail implementation
  • Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
  • Strong experience with Synopsys EDA tools including understanding of their capabilities and underlying algorithms
  • Strong knowledge of deep sub-micron FinFET and CMOS solid state physics
  • Strong knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
  • Deep understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
  • Familiar with CMOS analog circuit and physical design
Job Responsibility
Job Responsibility
  • Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
  • Develop/improve physical design methodologies and automation scripts for various implementation steps
  • Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
  • Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution/timing/congestion and flow issues, identify potential solutions and drive execution
  • Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop
  • Fulltime
Read More
Arrow Right

Physical Design Engineer

This is a hybrid role with four days per week at Cisco’s Yerevan office. Step in...
Location
Location
Armenia , Yerevan
Salary
Salary:
Not provided
duo.com Logo
Duo Security
Expiration Date
Until further notice
Flip Icon
Requirements
Requirements
  • Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field
  • 6+ year minimum of hands-on experience in ASIC design and verification
  • Proven expertise in ASIC physical design and verification with a strong track record of delivering complex projects
  • Advanced knowledge of block-level synthesis, place-and-route (PnR), and timing closure
  • First-hand experience with industry-standard PnR and signoff tools such as Synopsys and Cadence
Job Responsibility
Job Responsibility
  • Drive macro level RTL to gds implementation and signoff
  • Work with Front-End teams to understand the design architecture to ensure optimal physical implementation
  • Execute critical physical design tasks, including gate-level netlist synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), and routing
  • Optimize designs to achieve industry-leading power, performance, and area (PPA) metrics while maintaining design integrity through formal verification
  • Conduct Static Timing Analysis (STA), physical verification, formal verification and signoff closure to ensure high-quality results
  • Analyze and resolve Electromigration (EM) and IR-drop (IR) issues, meeting stringent signoff requirements for reliability and performance
Read More
Arrow Right