This list contains only the countries for which job offers have been published in the selected language (e.g., in the French version, only job offers written in French are displayed, and in the English version, only those in English).
This is an outstanding opportunity for an experienced engineer passionate about circuit power optimization to apply their skills to high-speed SerDes (Serializer/Deserializer) systems. As part of a team, you will evaluate and optimize advanced DSP algorithms and circuits for 200+Gbps SerDes for lowest static and dynamic power consumption. Your work will directly impact the performance of AMD’s next-generation connectivity solutions for markets such as data center networking and wireless telecommunications.
Job Responsibility:
Collaborate with architects, hardware engineers and verification engineers to define, refine and implement low power DSP features for cutting-edge and next-generation SerDes transceivers
Model and evaluate equalization, filtering and sequence detection algorithms for power efficiency
Contribute to RTL development, using front-end ASIC tools to ensure the highest quality code
Contribute to power testcase creation with verification engineers
Develop comprehensive documentation detailing power optimization approaches
Requirements:
Proven experience in power analysis and optimization of digital logic at advanced process nodes
Strong background in digital design techniques, RTL (preferably SystemVerilog)
Experience with PowerArtist and/or PPRTL tools, scripting and flows
Familiarity with ASIC front-end design tools and flows, in particular vectored power analysis and gate-level simulation
BSc or Masters in Electronics, Electrical or Computer Engineering, or related field
Nice to have:
Familiarity with equalization techniques such as FFE, CTLE, DFE or MLSE and their implementation