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Silicon Design Engineer

AMD

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Location:
Taiwan, Hsinchu ▼

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Category:
IT - Software Development

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Contract Type:
Not provided

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Salary:

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Job Description:

Be part of AMD IO IP team, joining IP design work on host controller IP for the next generation of leading-edge super high-speed IO, up to 40 Gb/s. Establishes and maintains AMD's high-speed IO technological leadership position.

Job Responsibility:

  • Takes part in host controller development based on architectural requirements for next-generation IO
  • Works on STA tasks such as defining clock architecture, creating SDC and exceptions, and analyzing timing reports
  • Works on RTL code development for IP blocks in Verilog HDL to ensure functionality is correct and reusable for multiple product lines
  • Deals with complex problems in both STA and RTL
  • Makes technical decisions
  • Coaches and mentors junior staff

Requirements:

  • Expert in Static Timing Analysis, familiar with DC, PT, GCA, and commands, worked in timing closure tasks with high clock frequency
  • Expert in Verilog RTL design on large-scale digital IP
  • Good English communication, presentation, and documentation
  • Work is performed with limited supervision. Strong sense of task scheduling and delivering on time as predetermined milestones committed to the manager
  • Can solve complex, novel, and non-recurring problems
  • Major in EE, CS or related, Master Degree or Bachelor with solid working experiences

Nice to have:

  • Specialized knowledge of USB2/3/4 or Thunderbolt specifications is a plus
  • Specialized knowledge of PCIe or AMBA protocol is a plus

Additional Information:

Job Posted:
December 17, 2025

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