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Senior Analog Design Engineer

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Microsoft Corporation

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Location:
India , Bangalore

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Category:
IT - Software Development

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Contract Type:
Not provided

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Salary:

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Job Description:

The Interface & Custom Circuit Engineering team in AI-Silicon Engineering is seeking experienced, passionate, driven, and intellectually curious Senior Analog Design Engineer who can work with cross-discipline teams (architecture, design, layout, verification, silicon-validation etc.) to develop High-speed Interface and analog-Mixed-Signal IPs for the SOCs of Microsoft.

Job Responsibility:

  • Lead Analog designs and delivery of cutting edge, high-performance, high-speed, low-power Analog IP designs for interconnectivity solutions and fundamental Analog circuit blocks for various Microsoft products in various process nodes including deep FinFet, following industry best practices
  • Technically deliver complex blocks that will produce schematics, verify in simulation, complete timing/jitter/power budgets and work with mask layout teams to deliver a final IP GDS
  • Coordinate tasks with junior members of the team, develop plans for Analog IP execution, follow processes/methodologies to deliver IP blocks
  • Coordinate bench validation of IP in Silicon, and IP characterization on bench and tester
  • Use established flows/methodologies/processes for execution
  • Work along with other members of the team to deliver IP’s, including project planning, schedule tracking, report generation
  • Interface with RTL, Verification and P&R team

Requirements:

  • BSEE or equivalent, MSEE/PhD preferred
  • 7+ years of experience in analog circuit design, through full cycle post BSEE or equivalent
  • Experience with high-speed analog front-end serdes or D2D design (preferably PCIe, UCIe, D-PHY, USB), data-converters, PLLs, Regulators and all associated blocks in analog designs from architecture till silicon validation support
  • Experience in Design partitioning, power/jitter budgeting and timing analysis
  • Knowledge of lower power design techniques, calibration, parasitic extraction, EM/IR/ESD/Aging & Signal Integrity Design
  • Experience with the use of CAD-tools (Cadence, Mentor, Synopsys) for circuit schematic entry, simulations, post layout extractions, Mixed-mode simulations
  • Delivered Analog IP’s successfully in mass production in FinFET processes
  • Experience in mentoring individual engineers
  • Working with multiple stakeholders (arch/design/layout/silicon validation/project managers) to execute full design cycle till silicon
  • Excellent communication skills and self-motivated that can collaborate with larger teams within Microsoft
  • Energetic and self-motivated and innovative problem solver
  • Ability to meet Microsoft, customer and/or government security screening requirements are required for this role

Nice to have:

  • Scripting language such as Python, Perl
  • Matlab modelling
  • Exposure to RTL behavioral modelling of analog blocks will be a plus
  • Masters or PhD degree from premier institutes

Additional Information:

Job Posted:
February 13, 2026

Employment Type:
Fulltime
Work Type:
Hybrid work
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