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Physical Design Engineer

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AMD

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Location:
China , Beijing

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Category:
IT - Software Development

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Contract Type:
Not provided

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Salary:

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Job Description:

In this role, you will be responsible for the implementation and signoff of complex digital integrated circuits from RTL to GDSII, focusing on cutting-edge process technologies. You will work closely with frontend design, DFT, and CAD teams to achieve power, performance, and area (PPA) targets while ensuring schedule adherence.

Job Responsibility:

  • Collaborate with architects, hardware engineers, and firmware engineers to understand the new features
  • RTL-to-GDSII Implementation – Execute full physical design flow including synthesis, floorplanning, placement, CTS, routing, and signoff
  • Timing & Power Closure – Perform static timing analysis (STA), power analysis, and optimize designs to meet timing, power, and area goals
  • Physical Verification – Run DRC, LVS, and other verification checks to ensure design manufacturability
  • Methodology & Automation – Develop and maintain scripts to improve design efficiency and quality
  • Cross-functional Collaboration – Work with frontend, DFT, and CAD teams to resolve design issues and implement methodology improvements
  • Documentation & Reporting – Create clear documentation and regularly report progress to project stakeholders

Requirements:

  • Full chip floorplan experience
  • Scripting language experience: Perl, Tcl, Python
  • Exposure to leadership or mentorship is an asset
  • Experience with high-performance CPU/GPU/AI accelerator physical design in advanced nodes (7nm and below)
  • Hands-on experience with low-power design techniques (power gating, multi-voltage, DVFS) and UPF/CPF flow
  • Familiarity with 3D-IC or chiplet-based design methodologies and associated tool flows
  • Knowledge of package-aware floorplanning and system-level co-design considerations
  • Experience with machine learning applications in physical design (e.g., auto-placement, routing prediction)
  • Prior exposure to design for testability (DFT) integration and post-silicon debug support
  • Proven track record of successful tape-outs in high-complexity SoC projects
  • Bachelors or Masters degree in computer engineering/Electrical Engineering

Additional Information:

Job Posted:
February 13, 2026

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