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The Datacenter Graphics and Accelerated Computing Validation Team seeks a proactive lead for our post-silicon validation group. The Memory sub-system validation lead oversees pre- and post-silicon validation and characterization of High-Bandwidth Memory (HBM) in AMD’s Datacenter GPU and large-scale systems. This role connects DRAM architecture, memory controller design, PHY, product engineering, and software teams to ensure advanced memory technologies meet AMD’s quality standards from design through production.
Job Responsibility:
Oversee planning, execution, and debugging across all stages of pre- and post-silicon validation
Create and carry out test plans for HBM functional and electrical validation, including PVT Shmoo characterization
Requirements:
Extensive experience in SoC validation, verification, and debugging of High-Bandwidth Memory subsystems
Lead functional and electrical validation plans development for memory features with cross-functional teams
Lead post-silicon debug, identify root causes, and guide corrective actions by partnering with stakeholders
Collaborate on memory-related silicon issues with Design, Verification, Silicon Validation, Manufacturing teams
Proficient with industry-standard tools: JTAG, I2C, Testers, and lab equipment
Strong programming skills (C/C++, Python) on Linux and Windows platforms
Effective team player, skilled at multitasking in fast-paced environments
Bachelors or Masters in Electrical or Computer Engineering