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BAE Systems is seeking an FPGA Design Manager to work within our Electronic Systems business area leading an FPGA Design group. We are interested in candidates with leadership, project management, and FPGA design experience, who have had a role in new development and/or established programs. Candidates must demonstrate strong technical aptitude and leadership skills. Experience leading design engineers within multi-disciplined engineering teams through all phases of an ASIC or FPGA development lifecycle is important, as the individual will be in a position to influence program execution and mentor engineers.
Job Responsibility:
Leading and managing a team of FPGA Design engineers
Hiring and staffing design engineers in support of program needs
Advancing the state of FPGA design at BAE Systems by assessing and evaluating modern tools, design techniques, and hardware resources
Managing personnel performance and development
Influencing program execution, and scope management
Communicating information to engineering team, up through leadership, and across the organization for sharing of best practices and lessons learned
Assisting in the development, review, and approval of proposals, and negotiating scope with programs
Enhancing engineering processes used on programs, and ensuring consistent application of those processes
Supporting key initiatives to improve the business execution or discipline
Requirements:
10+ years of relevant experience with bachelor's degree in EE/ECE
Current Security Clearance (Secret or higher), or eligible to obtain one
Experience leading and managing FPGA/ASIC design teams
Proficient in planning and managing schedule, staffing, cost, and risks
Flexibility to work in a dynamic environment with changing needs, requirements, and technical challenges
Ability to provide mentorship to less experienced team members
Strong written and oral communication skills
Deep understanding of FPGA architecture and design tradeoffs
Experienced in all stages of FPGA and/or ASIC development including requirements management, RTL design, synthesis, timing analysis, lab bring up/validation
Proficient in VHDL (preferred) or Verilog HDL coding
Familiarity with AMD (Xilinx) Vivado or Altera (Intel) Quartus
Proficient in MS-Project, MS-Word, MS-Excel
Nice to have:
Masters degree in EE/ECE or technical MBA with 10+ years of experience
Experience with Matlab and DSP fundamentals
Software development skills (C/C++)
Scripting skills (Perl, Python, bash, Tcl)
Exposure to Design Verification methodologies such as UVM/OVM
Experience with Earned Value Management is a plus
Experience with DoD projects
What we offer:
Flexible work environment
Competitive benefits
Health, dental, and vision insurance
Health savings accounts
401(k) savings plan
Disability coverage
Life and accident insurance
Employee assistance program
Legal plan
Discounts on home, auto, and pet insurance
Paid time off
Paid holidays
Paid parental, military, bereavement, and applicable federal and state sick leave