ASIC Principal Design Engineer Job at Hewlett Packard Enterprise (Bangalore)

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly skilled and experienced Principal Engineer to join our A...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

BE or Master's in Electronics or Electrical Engineering, Computer Engineering, or a related field
8+ years of experience in ASIC development, with a proven track record of leading complex project
Hands on in IP / blocks / subsystem complex design in verilog / sysverilog
Strong digital design development and execution skills , solving bugs
Experience in grooming team of 1-4 engineers, interacting with many team
Deep expirience in debug , solving problem, see the architecture view, proposing solutions.
Hands-on experience with industry-standard EDA tools and design flows
Deep knowledge on PCIe, axi , DMA, AHB interfaces
Expertise in high-performance and low-power design techniques
Excellent communication skills, both verbal and written, with the ability to articulate complex technical concepts clearly

Job Responsibility

Design and implements IPs and subsystems
Dealing the best of class IPs for all SanDisk products

Fulltime

Principal Technical Marketing Engineer

As a Principal Technical Marketing Engineer at Hewlett Packard Enterprise, you w...

Location

United States , Roseville

Salary:

148000.00 - 340500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Min. 15+ years of networking, security, telemetry, and automation experience
Min. 5+ years of TME experience
Security certification will be plus
Data Center certification will be plus
Excellent knowledge of Data Center Networking designs, architectures
Excellent knowledge of data center networking security, telemetry, and automation
Data Center deployment experience such as HPE or Dell EMC hyper converged solution, HPE Storage and Compute
Advanced networking knowledge such as BGP Based EVPN, EVPN-VXLAN
Advanced security knowledge such as IPsec, NAT, IDS, IPS, DDoS and NG-Firewall
Advanced telemetry knowledge such as IPFIX, gNMI, gRPC, Automation

Job Responsibility

Develop compelling demonstrations that best showcase HPE Aruba Networking industry-leading solutions for Security-first AI Powered Networking
Serve as the Aruba Switching authority and key technical advisor/guide for Aruba Enterprise Switching Products and Solutions
Create technical Enterprise Switching Architectures, Webinars, Videos, Documents/Collaterals, Podcasts, Blogs, Social media posts, Presentations, Resource Guides / Playbooks, Newsletters & email blast content, Webpages, and demonstrations for Aruba Switching platforms and solutions
Track and identify product solution gaps, competitive differentiation, and link outputs to marketing collateral and engineering developments
Learn and engage with SE/CSE/Customers, enhance knowledge and building subject-matter expertise (SME)
Create examples of use cases and network deployments, highlighting Aruba Switching’s unique value proposition
Develop 'deep-dive' technical presentations used by Aruba’s Pre-Sales Engineering team, Channel and Service Provider partners
Reinforce Core Product Managers in prioritizing Customer NFRs and writing PRDs
Assist System Engineers, Marketing, Sales teams with deep-dive technical presentations, roadmap updates and product demonstrations in selective engagements and for very large Opportunity engagements

What we offer

Extensive benefits
Competitive salary
Flexible work-life balance
Career growth programs
Diversity, inclusion, and belonging initiatives
Health and wellbeing support

Fulltime

Principal Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Mountain View

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
This role will require access to information that is controlled for export under export control regulations
10+ years expertise in Digital Design including microarchitecture specification development, RTL coding in Verilog/System Verilog and Clock Domain Crossing (CDC)/Lint closure
8+ years of experience delivering successful IP or Application Specific Integrated Circuits (ASIC)/SOC designs
5+ years of experience in Synthesis, Timing constraints, Power, Performance, Area (PPA) trade-offs and Post-Silicon Debug
5+ experience in Designing Fabric/Network On Chip or Networking ASICs or Complex Control Logic

Job Responsibility

Part of the design team driving many facets of high performance, high bandwidth designs
Working on Intellectual Property (IP) microarchitecture specification, Register Transfer Level (RTL) design, synthesis, and System on Chip (SOC) integration on different subsystems
Interacting with various teams, including architecture, verification, and physical design, ensuring that the design is implemented and verified to the spec

Fulltime

Principal Logic Design Engineer

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Raleigh

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
This role will require access to information that is controlled for export under export control regulations
As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status
To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport

Job Responsibility

Establish yourself as an integral member of a digital logic design team for the development of AI components with focus on micro-architectural based functions and features
Be responsible for the logic design/Register Transfer Level (RTL) entry, design quality including Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC), power etc., and timing closure of high-performance digital IP
Collaborate with the verification team to ensure the implementation meets both architectural and micro-architectural intent
Interface with physical design (PD), design for test (DFT), and other teams to optimize tradeoffs within the design
Provide technical leadership through mentorship and strong teamwork

Fulltime

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly experienced and motivated Principal Engineer specialisin...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field
9+ years of experience in digital design, with a focus on RTL design for complex SoCs
Deep expertise in Verilog/SystemVerilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Experience with synthesis, static timing analysis, and DFT concepts
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Proven track record of leading technical teams and delivering successful silicon
Excellent analytical, problem-solving, and communication skills
Passion for innovation and delivering high-quality, scalable solutions

Job Responsibility

Define and review SoC architecture and design specifications
Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog
Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab
Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering
Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement
Technical Excellence: Drive integration and debug efforts for subsystem and full-chip level. Analyse design trade-offs and guide design optimisations for area, performance, and power
Contribute to IP selection, evaluation, and integration in SoC designs
Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment across all levels

Fulltime

Principal Engineer, ASIC Development Engineering (RTL Design)

We are seeking a highly experienced and motivated Principal Engineer specialisin...

Location

India , Bengaluru

Salary:

Not provided

Sandisk

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical/Electronic Engineering or related field
9+ years of experience in digital design, with a focus on RTL design for complex SoCs
Deep expertise in Verilog/SystemVerilog
Strong understanding of SoC architecture, AMBA protocols (AXI/AHB/APB), interconnects and peripherals for debug
Experience with synthesis, static timing analysis, and DFT concepts
Hands-on with EDA tools (simulation, lint, CDC, synthesis, formal verification)
Proven track record of leading technical teams and delivering successful silicon
Excellent analytical, problem-solving, and communication skills
Passion for innovation and delivering high-quality, scalable solutions

Job Responsibility

Define and review SoC architecture and design specifications
Develop high-quality RTL which is synthesizable using Verilog/SystemVerilog
Ensure robust design methodologies, including lint, CDC, RDC and FC-Elab
Drive Cross-Functional Collaboration: Partner with SoC Design, Verification, Validation, DFT, Physical Design, Mixed-Signal IP, Foundry, Hardware, Firmware, and Test Engineering
Mentor and Inspire: Provide technical leadership and mentorship to engineering teams, fostering a culture of innovation, accountability, and continuous improvement
Technical Excellence: Drive integration and debug efforts for subsystem and full-chip level. Analyse design trade-offs and guide design optimisations for area, performance, and power
Contribute to IP selection, evaluation, and integration in SoC designs
Communicate with Impact: Deliver clear, concise, and transparent project updates to stakeholders, ensuring alignment across all levels

Fulltime

Principal Physical Design Manager

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Raleigh

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
Ability to meet Microsoft, customer and/or government security screening requirements
Ability to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter
Ability to provide proof of country of citizenship or proof of US residency or other protected status for export control assessment
Bachelor's or master’s in electrical or computer engineering or related field with 10+ years of experience
Experience in physical design implementation, signoff at block / sub system / sub-chip / SoC level
Experience in tapeout of complex ASICs in leading edge process node technology
8+ years of hands-on experience in EDA vendor tools such as Fusion Compiler, VCLP, Primetime, Formality, or Cadence Innovus and Conformal

Job Responsibility

Lead a team in defining implementation and execution plan for a schip/SOC
Execute the plan for successful tapeout by working with various stakeholders (RTL, IP, Methodology, DFT, Architecture etc)
Drive the team to achieve the best performance, power, and area (PPA) for AI system-on-chips (SOCs)
Optimizing technology, libraries, physical design, RTL design, and architecture
Collaborate with various stakeholders such as RTL designers, IP teams, Methodology experts, DFT engineers, and Architects
Provide technical guidance and mentorship to team members
Oversee the development and implementation of physical design flows and methodologies
Collaborate with cross-functional teams to address design challenges and optimize for manufacturability
Monitor progress, identify risks, and implement mitigation strategies
Keep abreast of the latest industry trends, tools, and techniques in physical design

Fulltime

Principal Silicon Design Engineer

As CAD Manager you will be responsible for leading and optimizing the EDA enviro...

Location

Malaysia , Penang

Salary:

Not provided

AMD

Expiration Date

Until further notice

Requirements

10+ years of silicon EDA and/or digital ASIC design experience
PPA Power Performance Area Optimization
Virtuoso based custom Layout tools and flows
Calibre extraction flows, Totem & Redhawk for EM/IR
TCL, Python, PERL, or other scripting languages
2+ years in one or more of these tools: Design compiler, IC Compiler, Fusion Compiler, Cadence Virtuoso and Custom Compiler
Physical aspect of VLSI designs
Strong written and verbal communication skills
Bachelors or Masters degree in Computer Engineering/Electrical Engineering

Job Responsibility

Lead and manage the CAD infrastructure team supporting multiple IC design projects
Establish and maintain standardized design flows and methodologies
Implement and support customized CAD flows for Fabric design groups
Enable the team in meeting the design and development targets by working closely with external tool vendors
Develop tools flows methodologies on digital back-end domains, sign-off flows for timing, power, EM/IR, DRC/LVS/DFM, etc.
Improve engineering efficiency while improving design quality in IP release process
Be single point contact for bugs and issues for custom and analog physical design team
Build flow in TCL, Python to ensure quality and faster executions
Understand different methodologies used across industry to adopt best practices
Leverage and deploy AMD AI systems to design teams

ASIC Principal Design Engineer

Hewlett Packard Enterprise

Location:
India , Bangalore

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
February 21, 2026

Looking for more opportunities? Search for other job offers that match your skills and interests.

Similar Jobs for ASIC Principal Design Engineer