Asic Physical Design Engineer Jobs

New

Senior SoC/ASIC Physical Design Engineer

As a Senior SoC/ASIC Physical Design Engineer, you will work on developing and i...

Location

United States , Irvine

Salary:

Not provided

Xcelerium

Expiration Date

Until further notice

Requirements

5+ years of ASIC and/or physical design flow development experience
Experience with ASIC physical design, physical design flows and methodologies (i.e., synthesis, place and route, STA, formal verification, CDC or power analysis using industry standard tools)
Scripting experience with Python, Tcl, or Perl
Experience in extraction of design parameters, QOR metrics, analyzing trends, voltage scaling (SVS, DVFS), and SRAM split rail implementation
Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
Strong experience with Synopsys EDA tools including understanding of their capabilities and underlying algorithms
Strong knowledge of deep sub-micron FinFET and CMOS solid state physics
Strong knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
Deep understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
Familiar with CMOS analog circuit and physical design

Job Responsibility

Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
Develop/improve physical design methodologies and automation scripts for various implementation steps
Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution/timing/congestion and flow issues, identify potential solutions and drive execution
Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

Fulltime

New

Senior Physical Design Engineer

As a Senior Physical Design Engineer, you will be responsible for the physical i...

Location

United States , Batavia, Illinois

Salary:

Not provided

NHanced Semiconductors

Expiration Date

Until further notice

Requirements

US Citizenship
5+ years of experience in physical design, specifically in ASIC, SoC, or advanced packaging (2.5D, 3DIC) technologies
Hands-on experience with Git-based version control systems for managing design revisions
Experience with timing closure and signal integrity
Proficiency in Cadence tools for physical design, timing analysis, and signoff
Strong understanding of RTL-to-GDSII flows, including floorplanning, power planning, place-and-route, and timing closure
Working knowledge of parasitic extraction (PEX), power integrity (PI), and thermal analysis in multi-die environments
Ability to work independently with minimal supervision and drive tasks to completion
Excellent verbal and written communication skills for collaboration across engineering teams
Strong debugging skills and ability to analyze tool reports, logs, and simulation results

Job Responsibility

Drive full-chip physical implementation of 2.5D interposer and ASIC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization
Ensure design compliance with timing, power, and area (PPA) requirements, as well as DFM, DRC, and LVS constraints
Utilize Cadence tools (Innovus, Virtuoso, Tempus, Voltus, Pegasus, etc.) for physical design, verification, and signoff
Develop and execute timing closure strategies, working with STA engineers to meet performance goals
Optimize power distribution networks (PDN) and electromigration (EM) reliability in multi-die packaging environments
Work with package and system engineers to optimize die-to-die interconnect, bump placement, and TSV integration
Collaborate with RTL designers, DFT engineers, and backend teams to ensure seamless integration
Implement ECOs (Engineering Change Orders) and efficiently iterate design revisions
Utilize Git-based version control workflows for design database management and collaborative development
Identify and resolve congestion, signal integrity (SI), and crosstalk issues in complex designs

Physical Design Engineer

This role has been designed as ‘Hybrid’ with an expectation that you will work o...

Location

India , Bangalore

Salary:

Not provided

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

4+ years experience in ASIC physical design
Experience with block implementation, extraction, timing and or full-chip designs
Strong communication skills
Strong hands-on TCL/Perl development skills
Experience as a full-chip floorplanning, routing, or timing lead for a large silicon project
Track record of taping out complex chips on advanced process nodes

Job Responsibility

Responsible for all aspects of Physical Design for Fullchip/Blocks covering Floorplanning, Placement, Budgeting, Clock Tree planning & analysis, Scan re-ordering, Clock tree synthesis, Placement optimizations, Routing, Timing and SI analysis/closure, ECO tasks (both timing and functional), EM/IR, DRC, LVS, ERC analysis & fixes, Low Power solution development & implementation
Work closely with the methodology team to solve the implementation challenges & provide inputs to improve the Physical design flow
Experienced in design automation
Understanding of Timing constraints, SI prevention, Power reduction

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

ASIC Design Engineer

Join our dynamic ASIC design team at HPE Aruba Networking, where we’re building ...

Location

United States , Roseville

Salary:

89400.00 - 206500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field
0–4 years of experience in VLSI design, verification, or implementation
Strong understanding of digital logic, computer architecture, and VLSI fundamentals
Exposure to ASIC or FPGA design flows
Experience with Verilog/SystemVerilog and EDA tools (e.g., Synopsys, Cadence)
Familiarity with scripting languages (e.g., Python, Perl, Tcl)
Excellent communication skills and a collaborative mindset

Job Responsibility

Design and implement portions of computer/server architecture and algorithms using VLSI engineering principles
Simulate and verify RTL designs to ensure functionality, performance, and power goals are met
Collaborate with cross-functional teams including architecture, verification, and physical design
Participate in design reviews and contribute to continuous improvement of design methodologies
Communicate project status, technical challenges, and solutions with your team and leadership
Mentor and support junior engineers as needed

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

ASIC Design Engineer

Join our dynamic ASIC design team at HPE Aruba Networking, where we’re building ...

Location

United States , Roseville

Salary:

130500.00 - 300000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or equivalent
6–10 years of experience in VLSI design, verification, or implementation
Deep understanding of digital logic, computer architecture, and VLSI fundamentals
Proficiency in RTL design (Verilog/SystemVerilog), scripting (Python/TCL), and EDA tools (Synopsys, Cadence, etc.)
Strong analytical and problem-solving skills
Excellent verbal and written communication skills
Experience working in cross-functional or global teams

Job Responsibility

Lead project teams of internal and outsourced engineers through all stages of VLSI design—from architecture and RTL to validation and physical implementation
Drive architecture and logic design decisions, ensuring alignment with performance, power, and area goals
Review and evaluate designs for compliance with internal standards and industry best practices
Collaborate across functions to integrate VLSI components into broader system platforms
Provide technical leadership and mentorship to junior engineers
Champion innovation by integrating new technologies and methodologies into our design flows
Contribute to the selection and development of future technical leaders

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Asic Engineer

This role involves designing, analyzing, and developing ASIC hardware systems as...

Location

India , Bangalore

Salary:

Not provided

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

7+ years of ASIC design experience
Strong Verilog RTL coding skills
Knowledge of Synopsys Design Compiler, Verplex LEC, and Spyglass is desirable
Experience designing ASICs for networking protocols (Ethernet, FCoE) is a plus
Knowledge of high performance memory subsystems
Knowledge of multi-domain clock synchronization and high-speed serial interfaces
Strong problem solving and ASIC debugging skills
Excellent written and verbal communications skills
MSEE or BSEE is required

Job Responsibility

Define and architect high-performance blocks for the latest, most advanced networking ASICs
Perform micro-architecture and logic design to deliver maximum throughput, while using minimum power
Collaborate with the verification team in the development of the testplan and assist in debugging test failures
Collaborate with the physical design team to develop timing constraints, analyze timing violations, and perform timing fixes

What we offer

Comprehensive suite of benefits for physical, financial, and emotional wellbeing
Specific programs for career development
Open communications, empowerment, innovation, teamwork, and customer success culture
Pay for performance culture

Fulltime

VLSI Design Engineer

We are looking for a highly skilled VLSI Design Engineer to join global leader i...

Location

United Kingdom , Hampshire

Salary:

63000.00 - 73000.00 GBP / Year

BLUESTREAM PEOPLE

Expiration Date

Until further notice

Requirements

BSc degree in Electrical Engineering, Computer Science, or related field
Strong commercial experience in VLSI/ASIC engineering
Strong knowledge of the full VLSI chip-design flow and toolchain
Hands-on experience in RTL coding, verification, synthesis, and STA
Experience in VLSI architecture design
Solid understanding of signal processing and modem design (major advantage)

Job Responsibility

Develop digital modules from concept through to physical design implementation
Collaborate across teams to design and integrate advanced signal processing cores and subsystem solutions
Adapt and integrate subsystems into the company’s design environment
Drive design activities across RTL coding, verification, synthesis, and STA

What we offer

Negotiable for the right experience

Fulltime

ASIC Design Architect

We are seeking a highly experienced ASIC Networking Architect to join our archit...

Location

United States

Salary:

148000.00 - 340500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science. Ph.D. is a plus
Minimum 10+ years in ASIC architecture, with a focus on networking, computing, or high-performance data processing
Strong Background in: Computer Architecture: Multicore processing, memory hierarchy optimizations, hardware-software co-design
Networking Protocols: Ethernet, TCP/IP, BGP, MPLS, VXLAN, QoS, congestion control mechanisms
ASIC Development Lifecycle: RTL design (Verilog/SystemVerilog), verification methodologies (UVM), synthesis, P&R constraints, and tape-out experience
High-Speed Interfaces: PCIe Gen6, SerDes, CXL, HBM integration
Security & Virtualization: Hardware acceleration for secure packet processing, hypervisor optimizations, and virtual network functions
Leadership & Collaboration Skills: Experience working with cross-functional teams spanning hardware, software, and systems
Strong problem-solving and analytical abilities with a track record of delivering complex ASIC projects

Job Responsibility

Architecture Definition: Develop the micro-architecture and high-level design of networking ASICs, ensuring alignment with product goals, performance targets, and industry standards
Networking Protocols & Technologies: Design ASICs that support Ethernet (200G/400G/800G+), Programmability, and AI-driven networking enhancements
Computer Architecture & Memory Subsystems: Optimize packet processing pipelines, caching strategies, memory architectures (HBM, DDR, TCAM, SRAM), and interconnect fabrics for high-bandwidth, low-latency performance
ASIC Design Collaboration: Work with logic design, verification, and physical design teams to ensure smooth RTL implementation, synthesis, timing closure, and signoff
Performance Analysis & Optimization: Use simulation and emulation tools to model ASIC performance, validate system throughput, and optimize power/performance trade-offs
Security & Reliability Features: Implement security mechanisms such as MACSec, IPsec, and deep packet inspection for trusted networking solutions
Industry Trends & Future Technologies: Stay ahead of advancements in disaggregated networking, hardware acceleration (DPUs, SmartNICs), AI-driven networking, and software-defined infrastructure to influence long-term ASIC roadmaps
Technical Leadership: Drive architectural innovation and mentor engineers in design methodologies, ASIC lifecycle best practices, and system integration challenges
Influence Business decisions: Leverages recognized domain expertise, business acumen, and experience to influence decisions of executive business leadership, outsourced development partners, and industry standards groups

What we offer

Health & Wellbeing: We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing
Personal & Professional Development: We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division
Unconditional Inclusion: We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good

Fulltime

Asic Physical Design Engineer

Hewlett Packard Enterprise

Location:
United States, San Jose

Category:
-

Contract Type:
Employment contract

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
July 29, 2025

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Job Description:

Job Responsibility:

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Job Posted:July 29, 2025

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