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Asic Engineer Sr Staff

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Hewlett Packard Enterprise

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Location:
United States, San Jose

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Category:
IT - Software Development

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Contract Type:
Employment contract

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Salary:

148000.00 - 340500.00 USD / Year
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Job Description:

Hewlett Packard Enterprise is seeking a seasoned Design-for-Test (DFT) Engineer to develop cutting-edge networking silicon technologies. Responsibilities involve defining and implementing DFT architectures for ASICs, collaborating with design teams, conducting silicon failure analysis, and automating analysis workflows.

Job Responsibility:

  • define and implement DFT architecture for high-performance networking ASICs at 3nm and beyond
  • collaborate with RTL and physical design teams to integrate scan, compression, boundary scan, and MBIST features
  • develop and validate ATPG patterns for stuck-at, transition, and path-delay fault models
  • analyze and resolve DFT-related issues including ATPG DRC violations, simulation mismatches, and timing violations
  • apply test constraints and perform STA analysis to ensure timing closure in test modes
  • support silicon bring-up and ATE pattern validation using industry-standard formats (STIL, WGL, SVF)
  • conduct silicon failure analysis and contribute to system-level debug and yield improvement
  • automate DFT flows and analysis using scripting languages such as Perl and Tcl.

Requirements:

  • 10+ years of hands-on DFT experience in ASIC design, preferably in networking or high-speed digital domains
  • deep understanding of fault models: stuck-at, transition, path-delay
  • expertise in scan compression, ATPG, and MBIST architecture
  • experience with Siemens Tessent tools: SSN, JTAG, IJTAG, MBIST, and memory repair
  • proficiency with Synopsys tools: DFT Compiler, DFTMAX, Tetramax, Design Compiler
  • simulation experience with Synopsys VCS and Cadence NC-Verilog
  • timing analysis using PrimeTime and Cadence Tempus
  • able to define test constraints and review STA reports to ensure timing closure in test modes
  • debugging with waveform tools such as Novas and SimVision
  • familiarity with ATE pattern formats (STIL, WGL) and JTAG SVF
  • strong scripting skills in Perl and Tcl for automation and analysis.

Nice to have:

  • experience in silicon bring-up and system-level failure analysis for advanced process nodes (3nm and below)
  • familiarity with high-speed networking protocols and system-level test strategies
  • exposure to yield analysis and production test optimization.
What we offer:
  • health & wellbeing
  • personal & professional development
  • unconditional inclusion
  • competitive compensation, benefits, and career growth opportunities.

Additional Information:

Job Posted:
October 08, 2025

Employment Type:
Fulltime
Work Type:
Hybrid work
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