ASIC Engineer, Emulation Job at Meta (Sunnyvale)

Software Development Kit and Application Specific Integrated Circuit Systems Software Engineer III

Designs, develops, troubleshoots and debugs software programs for software enhan...

Location

United States , Roseville

Salary:

103400.00 - 237000.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor's or Master's degree in Computer Engineering, Computer Science, or equivalent
Typically, 4-6 years' experience
Extensive experience with multiple software systems design tools and languages: Real-time embedded OS, C, Rust, Go and Python
Experience to read the ASIC designs and understand them in detail
Experience working with Emulator and Simulator environments
Excellent analytical and problem-solving skills
Experience in overall architecture of software systems: Linux kernel drivers, Embedded Systems
Designing and integrating software systems running on multiple platform types into overall architecture
Evaluating forms and processes for software systems testing and methodology, including writing and execution of test plans, debugging, and testing scripts and tools
Excellent written and verbal communication skills

Job Responsibility

Designs enhancements, updates, and programming changes for portions and subsystems of systems software, including operating systems, compliers, networking, utilities, databases, and Internet-related tools
Analyzes design and determines coding, programming, and integration activities required based on general objectives and knowledge of overall architecture of product or solution
Writes and executes complete testing plans, protocols, and documentation for assigned portion of application
identifies and debugs, and creates solutions for issues with code and integration into application architecture
Leads a project team of other software systems engineers and internal and outsourced development partners to develop reliable, cost effective and high quality solutions for assigned systems portion or subsystem
Collaborates and communicates with management, internal, and outsourced development partners regarding software systems design status, project progress, and issue resolution
Represents the software systems engineering team for all phases of larger and more-complex development projects
Provides guidance and mentoring to less- experienced staff members

What we offer

Health & Wellbeing
Personal & Professional Development
Unconditional Inclusion

Fulltime

Power Methodology Engineer, Data Center Hardware IPs

A senior power lead for power architecture solutions, specializing in areas like...

Location

United States , Santa Clara

Salary:

191040.00 - 286560.00 USD / Year

AMD

Expiration Date

Until further notice

Requirements

Extensive industry experience, with a specialization in low-power-processor architectures or power management
Expertise in ASIC/SoC power analysis and optimization techniques
Working experience in dynamic and leakage power estimation, analysis, and reduction at various levels (architecture, RTL, circuit design)
AI/ML Concepts: Familiarity with machine learning algorithms and their application to power simulation/optimization, as well as an understanding of NPU function and AI workload characteristics
Proficiency in hardware description languages like Verilog or VHDL, and scripting
Strong analytical skills and experience with power analysis tools (e.g., PowerArtist, PTPX)
Expertise in hardware description languages (Verilog, VHDL), scripting (Python), and simulation/analysis tools
Strong analytical and problem-solving skills to tackle complex, multidisciplinary power and performance challenges
Several years of experience in dynamic and leakage power estimation, analysis, and reduction at various levels (architecture, RTL, circuit design)
Strong scripting and automation skills, preferably in Python

Job Responsibility

Focuses on optimizing the energy efficiency and power delivery of high-performance computing hardware used in large-scale AI and machine learning applications
Driving power methodology for AI-specific hardware components (like tensor cores and matrix multiplication engines) and using simulation tools (e.g., PowerArtist, PTPX) to estimate and optimize power consumption
Workload Optimization: Analyze the power and performance characteristics of AI, Graphics, Battery life WLs, especially specific WLs for NPUs, GPUs, and CPUs
Performance/Watt Optimization: Focus on maximizing performance while staying within strict power and thermal limits, which is critical for both data center and gaming applications
Power Optimization: Estimate and analyze power consumption at various stages of chip design (architecture, RTL, physical design)
Analysis and modeling: Creating power models and scripts for performance/power trade-offs
Methodology Development: Researching, developing, and deploying methodologies and automated flows (using scripting languages like Python or Perl) to enhance power analysis efficiency
Collaboration: Working with other teams, including RTL, Architecture, Physical Design, Emulation, software, Firmware to ensure power requirements are met across the hardware-software stack
Leadership: Mentoring junior team members and providing technical leadership on complex projects

Fulltime

Senior Verification Engineer

System Validation engineers in this group are responsible for driving validation...

Location

India , Bengaluru

Salary:

Not provided

ARM

Expiration Date

Until further notice

Requirements

4-6 Years of Experience
Bachelors (BS) or Masters (MS/MSc) in Electronics, Electrical or Computer Engineering
Experience of Emulation and system level validation for IPs and sub-systems and ASIC products
Emulation build skills and knowledge for a subsystem in at least one emulation system
Execution of the design in emulation platform and knowledge of hardware and software interplay
Knowledge of Validation test content using C, C++
Expertise on hardware behavioral language (Verilog, System Verilog)
Exposure to producing validation specifications and documentation describing sophisticated designs
Ability to work under time-scale pressure and meet ambitious targets without compromising on quality
Understanding of the fundamentals of computer architecture, system IP, memory subsystem, accelerator

Job Responsibility

Work with project team to understand, review the system requirements and deliver emulator testbench specifications
Own the development of validation platform in emulation, debug methodology, developing and implementing the test content, finding bugs, and running various validation checks for IPs (CPUs and SystemIPs), Interfaces (like CHI, PCIe etc.) in emulation environment
Guide other members of the team as needed to enable the successful completion of project activities

What we offer

Health and Wellness
Work and Life Success
Financial Rewards
Development and Support

Asic Engineer, Implementation

Meta Platforms, Inc. (Meta), formerly known as Facebook Inc., builds technologie...

Location

United States , Sunnyvale

Salary:

166000.00 - 198220.00 USD / Year

ASIC Design Architect

We are seeking a highly experienced ASIC Networking Architect to join our archit...

Location

United States

Salary:

148000.00 - 340500.00 USD / Year

Hewlett Packard Enterprise

Expiration Date

Until further notice

Requirements

Bachelor’s or Master’s degree in Computer Engineering, Electrical Engineering, or Computer Science. Ph.D. is a plus
Minimum 10+ years in ASIC architecture, with a focus on networking, computing, or high-performance data processing
Strong Background in: Computer Architecture: Multicore processing, memory hierarchy optimizations, hardware-software co-design
Networking Protocols: Ethernet, TCP/IP, BGP, MPLS, VXLAN, QoS, congestion control mechanisms
ASIC Development Lifecycle: RTL design (Verilog/SystemVerilog), verification methodologies (UVM), synthesis, P&R constraints, and tape-out experience
High-Speed Interfaces: PCIe Gen6, SerDes, CXL, HBM integration
Security & Virtualization: Hardware acceleration for secure packet processing, hypervisor optimizations, and virtual network functions
Leadership & Collaboration Skills: Experience working with cross-functional teams spanning hardware, software, and systems
Strong problem-solving and analytical abilities with a track record of delivering complex ASIC projects

Job Responsibility

Architecture Definition: Develop the micro-architecture and high-level design of networking ASICs, ensuring alignment with product goals, performance targets, and industry standards
Networking Protocols & Technologies: Design ASICs that support Ethernet (200G/400G/800G+), Programmability, and AI-driven networking enhancements
Computer Architecture & Memory Subsystems: Optimize packet processing pipelines, caching strategies, memory architectures (HBM, DDR, TCAM, SRAM), and interconnect fabrics for high-bandwidth, low-latency performance
ASIC Design Collaboration: Work with logic design, verification, and physical design teams to ensure smooth RTL implementation, synthesis, timing closure, and signoff
Performance Analysis & Optimization: Use simulation and emulation tools to model ASIC performance, validate system throughput, and optimize power/performance trade-offs
Security & Reliability Features: Implement security mechanisms such as MACSec, IPsec, and deep packet inspection for trusted networking solutions
Industry Trends & Future Technologies: Stay ahead of advancements in disaggregated networking, hardware acceleration (DPUs, SmartNICs), AI-driven networking, and software-defined infrastructure to influence long-term ASIC roadmaps
Technical Leadership: Drive architectural innovation and mentor engineers in design methodologies, ASIC lifecycle best practices, and system integration challenges
Influence Business decisions: Leverages recognized domain expertise, business acumen, and experience to influence decisions of executive business leadership, outsourced development partners, and industry standards groups

What we offer

Health & Wellbeing: We strive to provide our team members and their loved ones with a comprehensive suite of benefits that supports their physical, financial and emotional wellbeing
Personal & Professional Development: We also invest in your career because the better you are, the better we all are. We have specific programs catered to helping you reach any career goals you have — whether you want to become a knowledge expert in your field or apply your skills to another division
Unconditional Inclusion: We are unconditionally inclusive in the way we work and celebrate individual uniqueness. We know varied backgrounds are valued and succeed here. We have the flexibility to manage our work and personal needs. We make bold moves, together, and are a force for good

Fulltime

New

ASIC Verification - Team Lead

Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the...

Location

United States , Santa Clara

Salary:

139900.00 - 274800.00 USD / Year

Microsoft Corporation

Expiration Date

Until further notice

Requirements

Doctorate in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 3+ years technical engineering experience
Master's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 6+ years technical engineering experience
Bachelor's Degree in Electrical Engineering, Computer Engineering, Computer Science, or related field AND 8+ years technical engineering experience
equivalent experience
Ability to meet Microsoft, customer and/or government security screening requirements
Experience working with large verification projects, including cluster/subsystem and fullchip environments
Ability to lead large scale verification execution, driving multiple senior level verification engineers across geographic regions towards project completion
Develop comprehensive pre-silicon verification test plans based on design specifications and performance requirements
Create and maintain UVM/SystemVerilog-based testbenches for block-level, cluster-level, fullchip and emulation verification
Comfortable and experienced with AI based tools to accelerate productivity

Job Responsibility

Pre-Silicon Verification
Improves verification efficiency through new and updated methodologies or tools
Defines verification strategies and test plans
Owns verification of complex flows at the system on chip (SoC), subsystem (SS), or intellectual property (IP) levels
Drives the development of verification environments, runs, and debugs simulations to drive quality
Influences the product life cycle from definition to silicon, including writing test plans, developing tests, debugging failures and coverage signoff
Leads application of random-stimulus, coverage, formal verification, or other verification techniques to find bugs and meet test plan goals
Performance
Works collaboratively with various teams to define performance modeling requirements and ensure technology development planning meets needs
Determines type of performance model needed and appropriate model fidelity

Fulltime

ASIC Engineer - Infra Silicon Enablement

Meta is hiring ASIC Engineers within the Infrastructure organization. We are loo...

Location

India , Bangalore

Salary:

Not provided

New

ASIC Engineer, Infra Silicon Pre/Post Silicon Validation

Meta is hiring ASIC Engineers within the Infrastructure organization. We are loo...

Location

United States , Sunnyvale

Salary:

178000.00 - 250000.00 USD / Year

ASIC Engineer, Emulation

Meta

Location:
United States , Sunnyvale

Category:
IT - Software Development

Contract Type:
Not provided

Salary:

Job Description:

Job Responsibility:

Requirements:

Nice to have:

Additional Information:

Job Posted:
January 23, 2026

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Software Development Kit and Application Specific Integrated Circuit Systems Software Engineer III