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Analog Models & Verification Engineer, Architect

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Synopsis Engineering

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Location:
United States , Chandler

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Category:
IT - Software Development

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Contract Type:
Employment contract

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Salary:

181000.00 - 271000.00 USD / Year
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Job Description:

Synopsys software engineers are key enablers in the world of Electronic Design Automation (EDA), developing and maintaining software used in chip design, verification and manufacturing. They work on assignments like designing, developing, and troubleshooting software, leveraging the state-of-the-art technologies like AI/ML, GenAI and Cloud. Their critical contributions enable world-wide EDA designers to extend the frontiers of semiconductors and chip development.

Job Responsibility:

  • Work closely with analog circuit teams to extract all necessary details, simulate, and sign off on high-fidelity models by rigorous comparison with SPICE-level simulations and silicon data
  • Develop and refine behavioural models of the analog portions of high-speed SerDes blocks (TX/RX, ADC, DAC, CDR, CTLE/equalizer, VGA/amplifier, PLL, VCO, Phase Interpolator)
  • Ensure models accurately capture all relevant functionalities, calibration/adaptation controls, time- and mode-dependent behaviors, key performance aspects, and residual impairments (offsets, gain mismatches, jitter, noise, skew, supply noise, etc.)
  • Interface with digital design and verification teams to guarantee exhaustive model verification—ensuring all functionalities and edge-cases are included in regression and integration test plans
  • Reviewing execution against verification plans through regular meetings with multiple verification teams (analog, cosim, DV, GLS, formal, emulation)
  • Integrate behavioral models into modern verification environments (UVM, MS-MDV), utilizing assertion-based checks, analog/digital interface scoreboards, and power-aware techniques as appropriate
  • Optimize model implementations for simulation speed and accuracy
  • Drive continuous improvement and automation in the creation, maintenance, and validation of SerDes behavioral models
  • Establish and evangelize best practices and reusable frameworks for efficient, scalable RNM modeling and mixed-signal verification
  • Mentor and support teammates, sharing knowledge, methodology innovations, and documentation

Requirements:

  • BSc, MSc or PhD in Electrical/Computer Engineering, with 7+ years of relevant industry experience
  • Advanced proficiency with Verilog, SystemVerilog (including RNM, wreal modeling, and IEEE 1800-2012 SV-DC extensions)
  • Robust understanding of analog/mixed-signal SerDes sub-blocks: TX/RX, ADC, DAC, CDR, CTLE/equalizer, VGA/amplifier, PLL, VCO, Phase Interpolator
  • Proven ability to model analog circuit impairments: offsets, gain/mismatches, jitter, noise, skew, supply noise, etc.
  • Fluency with analog schematics, SPICE-level simulation tools and waveform analysis
  • Strong scripting/programming in Python, TCL, Perl, C/C++
  • Familiarity with verification flows: regression, analog/mixed-signal co-simulation, digital verification, gate-level simulation, formal methods, and emulation
  • Experience with UVM testbenches, assertion-driven and coverage-driven verification
What we offer:
  • Comprehensive medical and healthcare plans that work for you and your family
  • In addition to company holidays, we have ETO and FTO Programs
  • Maternity and paternity leave, parenting resources, adoption and surrogacy assistance, and more
  • Purchase Synopsys common stock at a 15% discount, with a 24 month look-back
  • Save for your future with our retirement plans that vary by region and country
  • Competitive salaries
  • Annual bonus, equity, and other discretionary bonuses

Additional Information:

Job Posted:
January 24, 2026

Employment Type:
Fulltime
Work Type:
On-site work
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