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Asic Physical Design Engineer Jobs

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Asic Physical Design Engineer
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Join our team in San Jose as an ASIC Physical Design Engineer. You will lead large SoC implementations from RTL to GDSII, focusing on floorplanning, power grid, and clock network design. We require 7+ years of experience in full-chip physical design and verification. We offer a comprehensive bene...
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United States , San Jose
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148000.00 - 340500.00 USD / Year
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Hewlett Packard Enterprise
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Until further notice
Staff Engineer, ASIC Development Engineering (Physical Design, Pnr, Floor Planning)
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Join our team in Bangalore as a Staff Engineer for ASIC Physical Design. You will own block-level floorplanning, place & route (PNR) for high-performance, low-power designs using tools like Fusion Compiler or Innovus. We seek an expert with 5+ years of PNR experience and knowledge of advanced nod...
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India , Bangalore
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Not provided
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Sandisk
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Until further notice
ASIC Engineer, Physical Design
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Join Meta's Infrastructure team as an ASIC Physical Design Engineer in Sunnyvale. You will own the physical implementation of high-performance, low-power SoCs from Netlist to GDSII in advanced nodes (5nm and below). This role requires expertise in large-scale designs (>20M gates, 1GHz+), EDA tool...
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United States , Sunnyvale
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146000.00 - 209000.00 USD / Year
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Meta
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Until further notice
Explore a world of opportunity in ASIC Physical Design Engineer jobs, a critical and highly technical field at the heart of modern electronics. ASIC (Application-Specific Integrated Circuit) Physical Design Engineers are the master builders of the semiconductor world. They take a logical circuit design, described in a hardware description language, and transform it into a physical, manufacturable blueprint—the GDSII file—that defines the intricate nanoscale patterns of a silicon chip. This role is the bridge between abstract electronic function and tangible, high-performance hardware, making it a cornerstone of innovation in everything from smartphones and data centers to automotive and AI systems. Professionals in this field are typically responsible for the entire physical implementation flow, often referred to as the RTL-to-GDSII process. A core initial task is floorplanning, where they determine the optimal placement of major functional blocks, input/output pins, and power distribution networks on the silicon die. Following this, they perform place and route (PNR), a complex process of placing millions of logic gates and then connecting them with wires, all while adhering to strict physical and electrical rules. A crucial sub-task is Clock Tree Synthesis (CTS), building a robust clock distribution network to ensure synchronous operation across the entire chip. Throughout this process, engineers must constantly analyze and optimize for multiple competing constraints: timing (meeting speed requirements), power (minimizing consumption and heat), and area (reducing silicon cost). They run extensive verification checks using specialized tools to debug and resolve issues like Design Rule Check (DRC), Layout vs. Schematic (LVS), and Electrical Rule Check (ERC) violations, ensuring the design is manufacturable. Implementing Engineering Change Orders (ECOs) to make final logic or timing fixes is also a common responsibility. Furthermore, they collaborate closely with front-end design, verification, and DFT (Design-for-Test) teams to integrate all components and ensure a successful tape-out—the final release of the design to the semiconductor foundry. To excel in these roles, a specific skill set is required. A bachelor's or master's degree in Electrical Engineering, Computer Engineering, or a related field is standard. Candidates need deep, hands-on experience with industry-standard Electronic Design Automation (EDA) tools from vendors like Cadence and Synopsys for synthesis, place and route, static timing analysis (STA), and physical verification. Proficiency in scripting languages such as TCL, Perl, and Python is essential for automating workflows and enhancing tool capabilities. A solid understanding of deep-submicron technologies (e.g., 7nm, 5nm, and below) and their unique challenges like signal integrity, electromigration, and IR drop is critical for successful sign-off. Strong analytical, problem-solving, and debugging skills are paramount, as is the ability to work collaboratively in a dynamic team environment. If you are passionate about creating the physical foundations of technology and thrive on complex, detail-oriented challenges, exploring ASIC Physical Design Engineer jobs could be the next step in your rewarding career.

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